1. Field of the Invention
The present invention relates to a wiring structure in a semiconductor wafer-scale integrated circuit (hereinafter referred to as IC).
2. Description of the Related Art
A wafer-scale IC comprises a plurality of identical functional blocks, each having memories and logic circuits for controlling thereof, and operates as a single device without separating these blocks. Therefore, the wafer-scale IC can integrate circuits of the largest scale, larger than any other ICs, and can reduce signal delay time due to its shorter length wirings between IC chips relative to that of conventional plural ICs each having an individual IC chip in a package. Moreover, since the assembling process required for individual chips is naturally unnecessary, the circuit fabrication processes can be simplified, and accordingly the device reliability can also be improved. Therefore, recent wafer-scale ICs provide memory capacity of 200M bits on a single wafer of 15 cm in diameter.
FIG. 1 schematically shows a plan view of a wafer-scale IC. A wafer 11 having 26 rows .times.9 columns of functional blocks 12 is mounted on a circuit board (not illustrated), formed of resin, etc., called a carrier. FIG. 2(a) is a plan view enlarging a part enclosed by dotted lines in FIG. 1. Each functional block 12 is fabricated by repeated exposures of a reticule of a single block, for rows and columns in a matrix, well known as a step and repeat method. Therefore, terminal electrodes (pads) 14 to supply a source voltage to each functional block are aligned on a line. Accordingly, power-supply layer-wiring 13 to supply the source voltage to each functional block is connected in series via the pads 14, and each pad 14 is connected in parallel to each functional block on line, as shown in FIG. 2(a). Wiring 13 is connected to the carrier (not illustrated) by a bonding wire via terminal electrodes (not illustrated) provided at the edge part of wafer 11, so as to receive the power source voltage. Power supply layer-wiring 13 is usually formed of a metal film pattern of about several tens of micron meters in width and about 1 .mu.m in thickness. As this power supply layer-wiring extends from the one edge to the other edge of the wafer of as large as 15 cm diameter, its resistance and inductance are both increased. Connection to the adjacent functional block is fabricated by overlapping the patterned wiring at the connecting areas during exposure for each functional block using the reticule. However, the reticule exposure of such a large pattern cannot easily establish the alignment accuracy at the peripheral part thereof, and the wafer itself does not always have sufficient surface flatness since many layers have been already fabricated thereon, resulting in a problem of reliability in comparison with the layer wiring usually formed by a single patterning. In order to avoid the problem, power supply terminals 14 of each functional block may be connected by a bonding wire 17 as shown in FIG. 2(b), in place of layer wiring 13. Since bonding wire 17 is typically formed of aluminum or gold of 30 to 100 .mu.m in diameter, its resistance and inductance can be remarkably lowered than layer wiring 13. However, even if a bonding wire is employed, since the power source voltage is supplied via the serially connected wirings to as many as typically twenty six functional blocks, a single wire-break causes no more power supply to all the functional blocks after the broken wiring point, resulting in a reliability problem of the device. The above explained structure, where the power supply wiring is only of a layer wiring or a bonding wire, is described in the U.S. patent application Ser. No. 359,677, issued Apr. 1, 1986 as U.S. Pat. No. 4,580,259 , assigned to the same assignee of the present invention. Thus, it has long been required to provide a method of supplying the source voltage to each functional blocks, while satisfying the high reliability requirement.